The Block Level Specification is an engineering
document that covers each one design blocks within
your chip. The number of block's that exist in your
design are based on the partitioning of your design.
Typically, a block will be a portion of your chip
design that can be handled by a single designer. If
done thoroughly, the block level spec should be the
only document necessary at the design review for the
block. The specs must follow a fixed format,
allowing consistency of information presented.
The content of the spec should have a major
section
for systems level information that covers the block
level functional description, testability, system
validation for the block, electrical performance
expectations, block level design scope and the
system level test bench. This portion of the
document should be completed by the system or chip
leader and should contain all the information
necessary for the transistor level designer to produce a design that
meets
the system level requirements.
A second major section should contain all the
transistor level information for the block. Typical
content would be the design approach chosen and why,
simulation
matrix run, models used, critical assumptions,
detailed design
description, schematics, simulation details
(schematics, stimulus and output), critical nodes,
post silicon
char data when available and any designer concerns.
If a block spec is completed in detail it serves
as
the agenda and content of your block level design
review. This
also has an added advantage of driving a fixed
format for
material at your design reviews. The audience will
know what to expect and where to find information
for each review. A 2nd benefit
of a fixed block spec template is that it becomes
the ideal documentation for your IP sharing
initiative. Everything in one place.
